The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. More particularly, the invention provides a novel trench isolation structure and method used for electrical isolation in semiconductor devices. Merely by way of example, the invention has been applied to the manufacture of dynamic random access memory (DRAM). But it would be recognized that the invention has a much broader range of applicability. For example, the invention can be applied to microprocessor devices, logic circuits, application specific integrated circuit devices, as well as various other structures.
As semiconductor devices have become highly integrated, patterns have become finer and a process for fabricating a shallow trench isolation (hereinafter, referred to as “STI”) structure having small width and excellent isolation characteristics has become increasingly important. The trench isolation structure affects the characteristics of a semiconductor memory device, such as a dynamic random access memory (DRAM). For example, a liner nitride film applied to the trench isolation structure improves the refresh characteristics of the DRAM. However, the liner nitride film can also exert a negative influence on peripheral circuit regions.
FIG. 1 is a sectional view illustrating a conventional method for fabricating a trench isolation structure in a semiconductor device.
With reference to FIG. 1, a pad oxide film pattern 110 and a pad nitride film pattern 120 are formed on a semiconductor substrate 100 having active regions and isolation regions. Then, trenches 125 and 130 having a predetermined depth are formed in the semiconductor substrate 100 by an etching process. A sidewall oxide film 140 is formed overlying the sidewalls of the trenches 125 and 130 by an oxidation process, and a liner nitride film 150 and a liner oxide film 160 are formed overlying the exposed surface of semiconductor substrate 100. Thereafter, an insulation film 170, for example, a high density plasma (HDP) oxide film, is formed overlying the mesa and trench regions so that trenches 125 and 130 are filled with insulation film 170. After a planarization process is performed to expose a pad nitride film 120 to the outside, the pad nitride film 120 and a pad oxide film 110 are sequentially eliminated, thereby completing the trench isolation structure. However, liner nitride film 150 traps hot electrons at peripheral circuit regions having p-type MOS transistors, and generates attractive force to holes on the surface of the active regions, thereby causing a hot electron induced punch-through (hereinafter, referred to as “HEIP”) reducing the channel width.
In the trench isolation structure shown in FIG. 1, liner nitride film 150 prevents an oxygen source from passing through the trench isolation structure in a subsequent oxidation process for forming a gate insulation film. It is well known to those skilled in the art that liner nitride film 150 causes reduction in the amount of leakage current and improves the refresh characteristics of a DRAM. However, liner nitride film 150 causes a reduction in a gapfill margin. In order to increase the gapfill margin, there is proposed a method, in which the deposition of the liner oxide film 160 is omitted and a preheating process is performed under an oxygen (O2) atmosphere.
In the case that the HDP oxide film is deposited on liner nitride film 150, the O2 flux is highest at bending portions (A) of the upper portion of the trench isolation structure during the preheating process and liner nitride film 150 at these portions is locally oxidized. When liner nitride film 150 at the bending portions (A) of the trench isolation structure is locally oxidized, the thickness of liner nitride film 150 at the bending portions (A) is thinned and boron (B) existing in the upper portion of the trench isolation structure is leaked to the outside, thereby causing a reduction in the threshold voltage. Further, as described above, liner nitride film 150 promotes the trapping of hot electrons at the peripheral circuit regions, and thus increases the occurrence of HEIP in p-type MOS transistors, thereby causing deterioration of characteristics of the semiconductor device, such as reduction in the threshold voltage and increase in leakage current in an OFF state.